1. Field of the Invention
The present invention relates to a data processing device and a bus access control method therein, and more specifically, to a data processing device including an internal bus connecting a computing circuit executing a program and a peripheral device and an internal bus connection circuit disabling an access from the computing circuit to the internal bus when an exception is occurred in the peripheral device, and a bus access control method in the data processing device.
2. Description of Related Art
In data processing devices such as micon, a multi-task processing is carried out, where a plurality of tasks are executed while switching them in time division. Further, the data processing device includes a computing circuit executing a task based on a program and a peripheral device connected to the computing circuit through a bus and executing various processings based on an instruction from the computing circuit. The peripheral device includes a memory, a coprocessor, and so on. The peripheral device may be embedded in the data processing device, or may be an external peripheral device provided outside the data processing device. In such a data processing device, when there is occurred an error (hereinafter referred to as exception) generated in the task to be executed or the peripheral device, the bus may be disabled to prevent tasks that are to be executed later from accessing the peripheral device improperly, so as to prevent the expansion of malfunction due to the exception.
One example of the data processing device including a means of disabling the bus is disclosed in Japanese Unexamined Patent Application Publication No. 2005-108222 (Biles). FIG. 16 shows a block diagram of a data processing device 100 disclosed in Biles. As shown in FIG. 16, the data processing device 100 includes a core 110, a memory 120, a bus 130, peripheral devices 140, and a reset controller 150. Further, the core 100 includes a processor 111, a cache 112, and a bus interface unit 113.
In the data processing device 100, the cache 112 is employed as a memory region in a processing executed in the processor 111. The cache 112 executes parity check of the data. When it is determined that the stored data is corrupted, the cache 112 outputs a corruption signal 151. The corruption signal 151 is transmitted to the bus interface unit 113 and the reset controller 150. The bus interface unit 113 to which the corruption signal 151 is input disables the access from the core 110 to the bus 130, so as to prevent the error from being transferred to the memory 120 and to the peripheral devices 140. The reset controller 150 resets the core 110. As such, it is possible to prevent the error from being transferred to the memory 120 and to the peripheral devices 140 in the data processing device 100.
Further, a method of disabling the connection between the computing circuit and the peripheral device in accordance with the occurrence of the exception is also disclosed in Japanese Unexamined Patent Application Publication No. 2003-50712. Further, a method of stopping the control of the peripheral device by the computing circuit without waiting for the process of the computing circuit when the exception is occurred in the peripheral device is disclosed in Japanese Unexamined Patent Application Publication No. 9-91210.